Introduction to RISC-V architecture Training Course
This course serves as an introduction to the RISC-V architecture and the microcontrollers built upon it. Participants may optionally engage in practical exercises using the GD32VF103 microcontroller, along with programming tasks in C or assembly language facilitated by the RARS simulator.
This course is available as onsite live training in Slovakia or online live training.Course Outline
Exploration of RISC-V architecture origins, the modular architecture definition encompassing base architectures and extensions, the RISC-V ISA including registers and the instruction set, features aligned with modern software concepts, and an overview of various RISC-V implementations.
RISC-V system architecture, exception handling mechanisms, the CLIC interrupt controller, and the ECLIC interrupt controller within the GD32VF103.
Exercises:
1. Firmware development for the GD32VF103 using VScode.
2. Implementation and management of GD32VF103 interrupts.
Requirements
Fundamental knowledge of the C programming language is required.
Open Training Courses require 5+ participants.
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Testimonials (1)
Being able to ask for advanced subjects even if there were not planned initially.
Gabriel Chouinard - Spark Microsystems
Course - FreeRTOS: Programming for Real Time Operating Systems
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