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Course Outline

Exploration of RISC-V architecture origins, the modular architecture definition encompassing base architectures and extensions, the RISC-V ISA including registers and the instruction set, features aligned with modern software concepts, and an overview of various RISC-V implementations.
RISC-V system architecture, exception handling mechanisms, the CLIC interrupt controller, and the ECLIC interrupt controller within the GD32VF103.

Exercises:
1. Firmware development for the GD32VF103 using VScode.
2. Implementation and management of GD32VF103 interrupts.

Requirements

Fundamental knowledge of the C programming language is required.

 7 Hours

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